European patent application No. EPA 0 152 116 to Hitachi shows a lateral transistor wherein a base region is formed in a raised, mesa type structure patterned in the surface of an N type epitaxial layer. P type emitter and collector regions are diffused into opposing sides of the base region via doped polysilicon regions formed adjacent the sides of the base region. The general structure of the raised-mesa type structure provides some inherent advantages over other lateral transistor structures, including the ability to form a highly symmetrical, narrow base region. This base region results in good transistor frequency response and gain characteristics.
The process shown and described in the above-referenced Hitachi application, however, includes several undesirable processing steps which make the process difficult and undesirable to practice. They also result in a less than optimum device. In particular, the process requires the growth of a thick, thermal oxide layer adjoining the bottom edges of the mesa structure under the subsequently formed polysilicon contacts. This thermal oxide results in substantial device stress and subsequent defects. Another disadvantage is the use of photolithographic techniques to define the device contacts. This limits the resolution of the lithography-defined structures, and subsequently limits the minimum size of the device. Other disadvantages of the Hitachi process and device will be discussed below.
U.S. Pat. Nos. 4,688,073 and 4,743,565, both to Goth et al., and both assigned to the assignee of the present invention, show a lateral transistor formed in a raised, semiconductor plateau. Collector and emitter regions are diffused into opposing sides of the plateau via a layer of doped polysilicon. The resulting structure, however, has the disadvantage of being non-planar, and of having device regions to which it is difficult to make contact.
U.S. Pat. No. 4,663,831 to Birrittella et al. shows a vertical bipolar transistor formed with L-shaped polysilicon contacts to the various device region.
U.S. Pat. No. 3,600,651 shows various transistor structures using polysilicon device contacts to single-crystal device regions.
IBM Technical Bulletin titled: "Lateral PNP with Gain Bandwidth Product", Vol. 13, No. 6, November 1970, page 1457, is of interest as showing a lateral PNP transistor. European patent application No. 0 052 038 to Fairchild Camera and Instrument Corp. is of interest as showing a lateral NPN transistor.